The Tech Library is a listing of technical papers, Conference Presentations, and articles that speak to hybridization techniques and challenges; they are listed with a short description to aid in your search.
Title | Date | Abstract | From |
Low Temperature Bonding of High Density Large Area Array Interconnects for 3D Integration |
IMAPS 2010 This material is posted here with permission of Imaps. |
The results of bonding and stress testing of Cu/Sn-Cu bonded dice and Cu-Cu thermo-compression bonded dice.... |
|
Embedded active device packaging technology for real DDR2 memory chips |
IWLPC October 2010 Originally published in the IWLPC Proceedings |
As high-speed, high-density, and high-performance are the primary IC development targets, packaging becomes key technology... |
|
Fabrication and performance of InAs/GaSb-based superlattice LWIR detectors |
SPIE Defense, Sensing & Security June 2010 Copyright 2010 SPIE |
InAs/GaSb-based type II superlattices (T2SL) offer a manufacturable FPA technology with FPA size, scalability and cost advantages over HgCdTe. |
|
Ultrathin 3D ACA FlipChip-In-Flex Technology |
ECTC June 2010 This material is posted here with permission of IEEE. |
Die thickness of common, high-volume chip stacks range between 50-100 µm while thinning industry aims towards ultrathin... |
Berlin Technical University, NB Technologies and Fraunhofer IZM. |
Three Chips Stacking with Low Volume Solder Using Single Re-Flow Process |
ECTC June 2010 This material is posted here with permission of IEEE. |
Miniaturized 3D package with shorter distances between chips are needed for the mobile and high frequency applications. |
|
Insertion Bonding: A Novel Cu-Cu Bonding Approach for 3D Integration |
ECTC June 2010 This material is posted here with permission of IEEE. |
A novel low temperature Cu-Cu bonding approach called the insertion bonding technique has been developed. |
|
Technical Bulletin N°3 |
February 2010 |
The SET Technical Bulletin is a compilation of technical articles written by our clients. Each article provides unique insights into the exciting area of C2W and C2C bonding. |
|
RF MEMS and flip-chip for space flight demonstrator |
June 2009 |
The next generation of telecommunication satellites payloads will require higher performances and higher.. |
|
Electrical characterization of high count, 10 µm pitch, room-temperature vertical interconnections. |
Imaps Device Packaging March 2009 This material is posted here with permission of Imaps. |
In order to increase the format of heterogeneous staring arrays to 2Kx2K pixels or even larger complexities, limited substrate size and cost... |
|
New Reflow Soldering and Tip in Buried Box (TB2) Techniques For Ultrafine Pitch Megapixels |
ECTC May 2008 This material is posted here with permission of IEEE. |
Flip chip is a high-density and highly reliable |
|
Title |
Date |
Abstract |
From |
NaPa "Library of Processes" |
January 2010 |
This FREE 152 pages book gives all directions needed to chose and apply an alternative nano-patterning technique: it is a must read for all! |
NaPANIL |
UV nanoimprint lithography process optimization for electron device manufacturing on nanosized scale |
November 2008 |
Imprint specific process parameters like the residual layer thickness and the etch resistance of the UV polymers for the substrate etch process have to be optimized to introduce UV nanoimprint lithography (UV NIL) as a high-resolution, low-cost patterning technique... |
IISB |
UV nanoimprint lithography process optimization for electron device manufacturing on nanosized scale |
September 2008 |
It's a poster |
|
UV nanoimprinting lithography using nanostructured quartz molds with antisticking functionalization |
February 2008 |
In this paper, we report the results obtained by the application of the SET FC150 equipment for UV-NIL... |
Title |
Abstract |
Presented at |
Author(s) |
3D-IC Integration using D2C or D2W Alignment Schemes together with Local Oxide Reduction |
3-Dimensional interconnection of high density integrated circuits enables building devices with greater functionality with higher performances in a smaller space. This paper explores the chip-to-chip and chip-to-wafer alignment and the associated bonding techniques such as in-situ reflow or thermocompression with a local oxide reduction which contributes to higher yield together with reduction of the force or temperature requirements. |
||
Flip-chip die bonding: an enabling technology for |
3-Dimensional Integration of Integrated Circuits is a method to build greater functionality into ever-smaller spaces for electronic circuitry, wherein dice of varying sizes, materials, or even application types are electrically and mechanically bonded together. |
IWLPC 2010 | |
Die-to-Wafer bonding of thin dies using a 2-Step approach; |
25 um thick dies, mounted on thick carrier die, were placed on a 300mm landing wafer using the High Accuracy Die Bonder SET-FC300. The bonding process was either Cu/Cu or Cu/Sn with respective pitch of 108 µm and 408 µm... |
Imaps Device Packaging 2010 |
SET's line of device bonders was formerly a division of SUSS MicroTec until its sale to SET management in 2007. SET North America (SETNA) was formed by several former employees of SUSS MicroTec to sell, service and support SET's device bonders. SETNA is the organizer and sponsor of DAAHTA and is also developing its own line of ancillary equipment to enhance device bonding.